The present invention relates to a semiconductor device and its manufacturing technology. More specifically, the invention concerns a semiconductor device forming a power transistor and a control integrated circuit on a single semiconductor chip and a technology effectively applied to the manufacturing technology of the semiconductor device.
A so-called discrete power transistor is composed of an independent power transistor and uses a thick film wiring because there is no need for forming complicated wiring. The use of the thick film wiring increases the wiring's cross section, making it possible to decrease the on-resistance. Further, the use of the thick film wiring can decrease a bonding damage that may be caused when a gold wire is bonded to a bonding pad. This makes it possible to arrange the power transistor under the bonding pad.
For example, Japanese Unexamined Patent Publication No. 2000-49184 (patent document 1) discloses the technology for discrete power transistors. This technology thickens a bonding wire connected to a source electrode of the power transistor and thins a bonding wire connected to a gate electrode.
The technology disclosed in Japanese Unexamined Patent Publication No. 2004-153234 (patent document 2) uses a thick metal strap for connection between the power transistor's source electrode and an external terminal and uses a thin metal strap for connection between the gate electrode and the external terminal.
There is available a standalone packaged semiconductor device that seals a semiconductor chip with a power transistor formed thereon and a semiconductor chip with a logic circuit formed thereon. Such semiconductor device concerns the technology described in Japanese Unexamined Patent Publication No. Hei 11 (1999)-204724 (patent document 3). The technology uses a thick bonding wire to connect a semiconductor chip for forming a power transistor and uses a thin bonding wire to connect a semiconductor chip for forming a logic circuit.
Further, there is a technology that forms a power transistor and a control integrated circuit on a single semiconductor chip. Such technology uses a bonding wire to connect the semiconductor chip with an external terminal (lead). The technology forms no device under the bonding pad so as to prevent damage during bonding.
[Patent document 1] Japanese Unexamined Patent Publication No. 2000-049184
[Patent document 2] Japanese Unexamined Patent Publication No. 2004-153234
[Patent document 3] Japanese Unexamined Patent Publication No. Hei 11 (1999)-204724